LiU » ELLIIT » 5G Wireless » WP4: Analog hardware

WP4: Analog hardware

Lead:
Atila Alvandpour (LIU)
Co-lead: Henrik Sjöland (LU)
 

Together with WPs we target a massive MIMO basestation. The cooperation will be especially intense
with WP1 and WP3. The targeted carrier frequency is 3.7GHz, to align with the present massive MIMO
testbed research at LU. We will develop hardware in form of integrated circuits (ICs), which can be used in
a demonstrator of a massive MIMO unit. The targeted architecture is a patch antenna array on a PCB, each
patch fed by an RF IC featuring antenna switch and a transceiver for TDD operation. The RF ICs in each row
of the antenna array are connected by single wire interfaces to an ADC/DAC IC, and each ADC/DAC IC is
connected through a high speed digital series interface to the central digital IC developed in WP3.

To avoid interference due to high frequency coupling between signal wires and antennas, the RF IC will
interface with the ADC/DAC IC using intermediate frequency (IF) signals. We have experience in this from
our successful IF over fiber work in the SSF project Distrant. Power saving in the ADC/DAC IC will be a key
objective and different modes will therefore be used during channel estimation and communication.